Information processing apparatuses attract attention in recent years, in which programmable devices, such as field programmable gate arrays (FPGAs), capable of dynamically reconfiguring logics are caused to function as accelerators. For example, in a print processing apparatus that converts input data into drawing data for printing, a pipeline including multiple processing stages that perform the conversion process into the drawing data is built by the programmable device. For example, related technology is disclosed in Japanese Laid-open Patent Publication No. 2000-255117.
In conversion of input data described in an object description language into intermediate data for each drawing object and rendering of the intermediate data into bitmap data, logics that perform the rendering process for each attribute of the drawing object are programmed into each block in the programmable device. The times to perform the rendering process in the respective blocks are made equal to each other by programming logics for the rendering process, in which the rendering process has not been completed, into blocks in which the rendering process has been completed to perform the rendering process. For example, related technology is disclosed in Japanese Laid-open Patent Publication No. 2006-88433.
In a typical image processing apparatus, any of multiple logics for image processing is programmed into the programmable device based on a feature of an image determined from an input image and the image processing is performed using the programmed logics. For example, related technology is disclosed in Japanese Laid-open Patent Publication No. 2008-242850.